1. Field of the Invention
The invention relates generally to the field of electronic circuitry and more specifically to phase-locked loop circuits for deriving data signals and timing signals from an input signal having both data and timing encoded therein.
2. Description of the Prior Art
Phase-locked loop circuits are used in many applications to derive a digital data signal and one or more timing signals from a single input signal, thereby obviating the need to provide separate timing signals along with the data input signal. The input signal is typically in the form of a pulse train, with the presence or absence of a pulse at a particular time indicating the value of a bit of digital data. The receiving units receiving the pulse train must receive the sequential pulses comprising the input signal, determine the proper timing relationships between consecutive pulses and from that determine whether a pulse is present or absent at the required time so as to identify the value of the digital data bit which is then being transmitted and transfer the bit to downstream processing circuitry. In addition, the receiving unit must generate timing signals which are used to clock the downstream processing circuitry.
Generally, a unit which transmits a data pulse train is designed to transmit the pulse train with a timing or frequency approximating a predetermined value, and the receiving unit is designed with timing circuits which assume the approximate timing value. However, because of timing tolerances which must be assumed in mass-produced equipment, the receiving units must allow for some variations in timing. Furthermore, and more important, receiving units must be able to accommodate a wide variation in phase of the incoming signal, since they cannot assume that the pulses will begin or end at any particular time.
Phase-locked loop timing circuits are used in receiving units to receive the incoming pulse stream and generate timing signals for use in decoding the pulse stream to derive the data signals therein. The frequencies of the timing signals generated by the phase-locked loop circuit are related to the particular optimal pulse frequency for which the transmitting circuits are also designed, but the frequencies may be adjusted up or down to accommodate the variations in timing which may be due to variations in the transmitting units. In addition, the phase-locked loop circuit may adjust the phases of the timing signals which it generates to accommodate the phase of the incoming pulse train.
Generally, a phase-locked loop circuit includes a voltage controlled oscillator which can generate a timing signal having a range of frequencies, generally centered around the frequencies at which the transmitting units are expected to generate the pulse train. The particular frequencies of the timing signals from the voltage controlled oscillator are related to the level of a control voltage applied thereto. A phase comparator compares the phase of the incoming pulse train with the timing signals from the voltage controlled oscillator and controls a charge pump which generates the control voltage applied to the voltage controlled oscillator. If an input pulse is early in comparison with timing signal from the voltage controlled oscillator, the frequency of the voltage controlled oscillator must be increased to, in part, advance the phases of the timing signal. Accordingly, the phase comparator enables the charge pump to adjust the control voltage so as to enable the voltage controlled oscillator to increase the frequencies of the timing signals generated thereby. The amount of adjustment of the control voltage, and thus, the frequency of the voltage controlled oscillator, is related to the time lag between the appearance of the pulse and the timing signal from the voltage controlled oscillator.
As the frequency of the voltage controlled oscillator increases, the rate at which timing pulses generated thereby also increases, and so the sequential pulses of the timing signal are transmitted earlier and earlier so as to more closely correspond to the timings of the pulses of the incoming data signals. As the timing signals from the voltage controlled oscillator get closer to the timings of the pulses, the phase comparator allows the control voltage to approach a steady-state level, allowing the frequency and phase of the voltage controlled oscillator to approach the frequency and phase of the incoming pulse train.
Similarly, if the pulses from the pulse train are delayed from the timing signals produced by the voltage controlled oscillator, the phase comparator enables the charge pump to adjust the control voltage applied to the voltage controlled oscillator to enable the voltage controlled oscillator to generate timing signals of lower frequency. Accordingly, the sequential pulses of the timing signals are delayed to match the timings of the sequential pulses of the input signal, thereby enabling the timing signals of the output of the voltage controlled oscillator to match the phase and timing of the pulses of the input signal.
The input data pulses and the timing signals from the voltage controlled oscillator are also used by a data separator which generates the actual data signal which is transmitted to the downstream processing circuitry. Since the data separator is the actual unit which uses the timing signals from the voltage controlled oscillator, it is desirable that the components thereof closely match the components of the phase comparator which is controlling the voltage controlled oscillator, otherwise the timing signals from the voltage controlled oscillator and the data output signal from the data separator are likely to become misaligned. Accordingly, the minimum pulse spacing of the input signal, which is related to the maximum data rate which the receiving unit may receive, is limited by the differences between the phase comparator and data separator and manufacturing tolerances in any receiving unit.